Renesas H8S/2319 series Hardware Manual page 204

Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH
is set to 1, an idle cycle is inserted at the start of the write cycle.
Figure 6-17 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
T
1
φ
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
(a) Idle cycle not inserted
(ICIS0 = 0)
Rev. 5.00, 12/03, page 174 of 1088
Bus cycle B
T T T T
2 3 1 2
Data
Long output
collision
floating time
Figure 6-17 Example of Idle Cycle Operation (2)
Bus cycle A
T
1
φ
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
(b) Idle cycle inserted
(ICIS0 = 1 (initial value))
Bus cycle B
T T T T
2 3 I 1
T
2