Register Configuration - Renesas H8S/2319 series Hardware Manual

8.6.2

Register Configuration

Table 8-9 shows the port A register configuration.
Table 8-9 Port A Registers
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register
Port A open-drain control register
Notes: 1. Value of bits 3 to 0.
2. Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
Bit : 7
—
Initial value : Undefined Undefined Undefined Undefined
R/W : —
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bits 7 to 4 are
reserved.
PADDR is initialized to H'0 (bits 3 to 0) by a reset and in hardware standby mode. It retains its
prior state after in software standby mode. The OPE bit in SBYCR is used to select whether the
address output pins retain their output state or become high-impedance when a transition is made
to software standby mode.
• Modes 4 and 5
The corresponding port A pins are address outputs irrespective of the value of bits PA3DDR to
PA0DDR.
• Mode 6 *
Setting PADDR bits to 1 makes the corresponding port A pins address outputs, while clearing
the bits to 0 makes the pins input ports.
Abbreviation
PADDR
PADR
PORTA
PAPCR
PAODR
6 5
— —
— —
Initial Value *
R/W
W H'0
R/W H'0
R Undefined
R/W H'0
R/W H'0
4 3
— PA3DDR PA2DDR PA1DDR PA0DDR
0
— W
Rev. 5.00, 12/03, page 249 of 1088
1
Address *
H'FEB9
H'FF69
H'FF59
H'FF70
H'FF77
2 1
0 0
W W
2
0
0
W