Table of Contents
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5.6
DTC Activation by Interrupt............................................................................................. 136
5.6.1
Overview.............................................................................................................. 136
5.6.2
Block Diagram..................................................................................................... 136
5.6.3
Operation ............................................................................................................. 137
6.1
Overview........................................................................................................................... 139
6.1.1
Features................................................................................................................ 139
6.1.2
Block Diagram..................................................................................................... 140
6.1.3
Pin Configuration................................................................................................. 141
6.1.4
Register Configuration......................................................................................... 142
6.2
Register Descriptions ........................................................................................................ 143
6.2.1
Bus Width Control Register (ABWCR)............................................................... 143
6.2.2
Access State Control Register (ASTCR) ............................................................. 144
6.2.3
Wait Control Registers H and L (WCRH, WCRL).............................................. 145
6.2.4
Bus Control Register H (BCRH) ......................................................................... 148
6.2.5
Bus Control Register L (BCRL) .......................................................................... 150
6.3
Overview of Bus Control .................................................................................................. 152
6.3.1
Area Partitioning.................................................................................................. 152
6.3.2
Bus Specifications................................................................................................ 153
6.3.3
Memory Interfaces ............................................................................................... 154
6.3.4
Advanced Mode................................................................................................... 155
6.3.5
Chip Select Signals .............................................................................................. 156
6.4
Basic Bus Interface ........................................................................................................... 157
6.4.1
Overview.............................................................................................................. 157
6.4.2
Data Size and Data Alignment............................................................................. 157
6.4.3
Valid Strobes........................................................................................................ 159
6.4.4
Basic Timing........................................................................................................ 160
6.4.5
Wait Control ........................................................................................................ 168
6.5
Burst ROM Interface......................................................................................................... 170
6.5.1
Overview.............................................................................................................. 170
6.5.2
Basic Timing........................................................................................................ 170
6.5.3
Wait Control ........................................................................................................ 172
6.6
Idle Cycle .......................................................................................................................... 173
6.6.1
Operation ............................................................................................................. 173
6.6.2
Pin States in Idle Cycle ........................................................................................ 176
6.7
Bus Release....................................................................................................................... 177
6.7.1
Overview.............................................................................................................. 177
6.7.2
Operation ............................................................................................................. 177
6.7.3
Pin States in External Bus Released State............................................................ 178
6.7.4
Transition Timing ................................................................................................ 179
6.7.5
Usage Note........................................................................................................... 180
6.8
Bus Arbitration.................................................................................................................. 180
Rev. 5.00, 12/03, page xvi of xxx
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