Renesas H8S/2319 series Hardware Manual page 933

Instruction Mnemonic
XOR XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
XORC XORC #xx:8,CCR
XORC #xx:8,EXR
Notes: 1. The number of state cycles is 2 when EXR is invalid, and 3 when EXR is valid.
2. When n bytes of data are transferred.
3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Branch
Instruction Address
Fetch Read
I J
1
1
2
1
3
2
1
2
Byte Word
Stack Data Data
Operation Access Access
K L M
Rev. 5.00, 12/03, page 903 of 1088
Internal
Operation
N