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10.3.3
Timing of TCNT External Reset
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 10-7
shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
10.3.4
Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 10-8
shows the timing of this operation.
φ
TCNT
Overflow signal
OVF
Rev. 5.00, 12/03, page 396 of 1088
N−1
Figure 10-7 Timing of Clearance by External Reset
H'FF
Figure 10-8 Timing of OVF Setting
N
H'00
H'00
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