Renesas H8S/2319 series Hardware Manual page 748

Renesas 16-bit single-chip microcomputer
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H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
Flash memory
EB8 to EB15
H'7FFFF
Figure 17-77 Example of a RAM-Overlap Operation
Figure 17-77 shows an example of an overlap on block area EB0 of the flash memory.
Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of
user MAT bank 0. The area is selected by the setting of the RAM2 to RAM0 bits in the RAMER
register.
(1) To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this
area, set the RAMER register's RAMS bit to 1, and each of the RAM2 to RAM0 bits to 0.
(2) Realtime programming is carried out using the overlaid area of RAM.
In programming or erasing the user MAT, it is necessary to run a program that implements a series
of procedural steps, including the downloading of a on-chip program. In this process, set the
download area with FTDAR so that the overlaid RAM area and the area where the on-chip
program is to be downloaded do not overlap. An FTDAR setting of H'02 will cause part of the
tuned data area to overlap with part of the download area. When using the initial setting of
FTDAR, the data that is to be programmed must be saved beforehand in an area that is not used by
the system.
Figure 17-78 shows an example of programming of the data, after emulation has been completed,
to the EB0 area in the user MAT.
Rev. 5.00, 12/03, page 718 of 1088
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
(user MAT)
This area is accessible as both a RAM
area and as a flash memory area.
On-chip RAM
H'FFBC00
H'FFDC00
H'FFEBFF
H'FFFBFF

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