Renesas H8S/2319 series Hardware Manual page 298

Port D Data Register (PDDR)
Bit : 7
PD7DR
Initial value : 0
R/W : R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to
PD0).
PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port D Register (PORTD)
Bit : 7
PD7
— *
Initial value :
R/W : R
Note: * Determined by state of pins PD7 to PD0.
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port D pins (PD7 to PD0) must always be performed on PDDR.
If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D
read is performed while PDDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTD contents are determined by the pin states, as
PDDDR and PDDR are initialized. PORTD retains its prior state in software standby mode.
Rev. 5.00, 12/03, page 268 of 1088
6 5
PD6DR PD5DR PD4DR
0 0
R/W R/W
6 5
PD6 PD5
— * — *
R R
4 3
PD3DR PD2DR
0 0
R/W R/W R/W
4 3
PD4 PD3 PD2
— * — *
R R
2 1
PD1DR PD0DR
0 0
R/W R/W
2 1
PD1 PD0
— * — * — *
R R
0
0
0
R