Table of Contents
Advertisement
9.2.6
Timer Counters (TCNT)
Channel 0: TCNT0 (up-counter)
Channel 1: TCNT1 (up/down-counter * )
Channel 2: TCNT2 (up/down-counter * )
Channel 3: TCNT3 (up-counter)
Channel 4: TCNT4 (up/down-counter * )
Channel 5: TCNT5 (up/down-counter * )
Bit
:
15
Initial value :
0
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * These counters can be used as up/down-counters only in phase counting mode or when
counting overflow/underflow on another channel. In other cases they function as up-
counters.
The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel.
The TCNT counters are initialized to H'0000 by a reset and in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
9.2.7
Timer General Registers (TGR)
Bit
:
15
Initial value :
1
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The TGR registers are 16-bit registers with a dual function as output compare and input capture
registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels
1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as
buffer registers * . The TGR registers are initialized to H'FFFF by a reset and in hardware standby
mode.
The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.
Rev. 5.00, 12/03, page 330 of 1088
14
13
12
11
10
0
0
0
0
14
13
12
11
10
1
1
1
1
9
8
7
6
0
0
0
0
0
9
8
7
6
1
1
1
1
1
5
4
3
2
1
0
0
0
0
0
5
4
3
2
1
1
1
1
1
1
0
0
0
1
Advertisement
Table of Contents
