Instruction Execution - Renesas H8S/2319 series Hardware Manual

Item
A.4 Number of States
Required for Instruction
Execution
Table A-5 Number of
Cycles in Instruction
Execution
A.5 Bus States during

Instruction Execution

Table A-6 Instruction
Execution Cycles
Rev. 5.00, 12/03, page x of xxx
Page Revision (See Manual for Details)
895, 897, "Advanced" deleted from Mnemonic column
901, 902
Instruction Mnemonic
BSR BSR d:8
BSR d:16
JMP JMP @ERn
JMP @aa:24
JMP @@aa:8
JSR JSR @ERn
JSR @aa:24
JSR @@aa:8
RTE RTE
RTS RTS
TRAPA TRAPA #x:2
903 Note 1 amended
The number of state cycles is 2 when EXR is invalid, and 3 when EXR is
valid.
909, 911, "Advanced" deleted from Instruction column
915, 916,
Instruction
917
BSR d:8 R:W NEXT
BSR d:16 R:W 2nd
JMP R:W NEXT
@@aa:8
JSR @ERn R:W NEXT
JSR @aa:24 R:W 2nd
JSR R:W NEXT
@@aa:8
RTS R:W NEXT
TRAPA #x:2 R:W NEXT
Reset R:W VEC
exception
handling
Interrupt R:W*
exception
handling
Instruc- Branch
tion Address
Fetch Read
I J
2
2
2
2
2 2
2
2
2 2
2
2
2 2
1 2 3 4
R:W EA W:W:M W:W
stack(H) stack(L)
Internal R:W EA W:W:M
operation, stack(H)
1 state
R:W:M aa:8 R:W: aa:8 Internal
operation,
1 state
R:W EA W:W:M W:W
stack(H) stack(L)
Internal R:W EA W:W:M
operation, stack(H)
1 state
R:W:M aa:8 R:W aa:8 W:W:M
stack(H)
W:W:M R:W Internal
stack(H) stack(L) operation,
1 state
Internal W:W W:W
operation, stack(L) stack(H)
1 state
5
R:W Internal R:W*
VEC+2 operation,
1 state
6
Internal W:W W:W
operation, stack(L) stack(H)
1 state
Stack Byte Word
Opera- Data Data
tion Access Access
K L M
2
2
2
2
2
2/3 *
1
2
2/3 *
1
5 6 7
W:W
stack(L)
R:W EA
W:W
stack(L)
W:W R:W EA
stack(L)
4
R:W*
W:W R:W:M VEC R:W Internal
stack(EXR) VEC+2 operation,
1 state
W:W R:W:M VEC R:W Internal
stack(EXR) VEC+2 operation,
1 state
Internal
Opera-
tion
N
1
1
1
1
1
1
2
8 9
7
R:W*
7
R:W*