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7.2.9
Module Stop Control Register (MSTPCR)
Bit
:
15
Initial value :
0
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
When the MSTP14 bit in MSTPCR is set to 1, DTC operation stops at the end of the bus cycle and
a transition is made to module stop mode. However, 1 cannot be written in the MSTP14 bit while
the DTC is operating. For details, see section 19.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 14—Module Stop (MSTP14): Specifies the DTC module stop mode.
Bit 14
MSTP14
Description
0
DTC module stop mode cleared
1
DTC module stop mode set
7.3
Operation
7.3.1
Overview
When activated, the DTC reads register information that is already stored in memory and transfers
data on the basis of that register information. After the data transfer, it writes updated register
information back to memory. Pre-storage of register information in memory makes it possible to
transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to
perform a number of transfers with a single activation. A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
Figure 7-2 shows a flowchart of DTC operation, and table 7-2 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
Rev. 5.00, 12/03, page 192 of 1088
MSTPCRH
14
13
12
11
10
0
1
1
1
9
8
7
6
1
1
1
1
1
MSTPCRL
5
4
3
2
1
1
1
1
1
1
(Initial value)
0
1
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