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16.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 16-1 shows the address and initial value of
SYSCR.
Table 16-1 RAM Register
Name
System control register
Note: * Lower 16 bits of the address.
16.2
Register Descriptions
16.2.1
System Control Register (SYSCR)
Bit
:
7
—
Initial value :
0
R/W
:
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 5.2.1, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Rev. 5.00, 12/03, page 548 of 1088
Abbreviation
SYSCR
6
5
—
INTM1
INTM0
0
0
—
R/W
R/W
R/W
Initial Value
R/W
H'01
4
3
2
NMIEG
LWROD
0
0
0
R/W
R/W
Address *
H'FF39
1
0
—
RAME
0
1
R/W
R/W
(Initial value)
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