Renesas H8S/2319 series Hardware Manual page 205

Relationship between Chip Select (CS
system's load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6-18.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A
T
1
φ
Address bus
CS (area A)
CS (area B)
RD
Possibility of overlap between
CS (area B) and RD
(a) Idle cycle not inserted
(ICIS1 = 0)
Figure 6-18 Relationship between Chip Select (CS
CS) Signal and Read (RD
CS CS
Bus cycle B
T T T T
2 3 1 2
RD) Signal: Depending on the
RD RD
Bus cycle A
T
1
φ
Address bus
CS (area A)
CS (area B)
RD
(b) Idle cycle inserted
CS) and Read (RD
CS CS
Rev. 5.00, 12/03, page 175 of 1088
Bus cycle B
T T T T
2 3 I 1
(ICIS1 = 1 (initial value))
RD)
RD RD
T
2