Renesas H8S/2319 series Hardware Manual page 376

Examples of Buffer Operation
• When TGR is an output compare register
Figure 9-19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details of PWM modes, see section 9.4.6, PWM Modes.
TCNT value
TGR0B
H'0200
TGR0A
H'0000
H'0200
TGR0C
Transfer
TGR0A
TIOCA
Rev. 5.00, 12/03, page 346 of 1088
H'0450
H'0200
Figure 9-19 Example of Buffer Operation (1)
H'0450
H'0520
H'0450
H'0520
Time