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12.2.7
Serial Status Register (SSR)
Bit
:
7
TDRE
Initial value :
1
R/(W) *
R/W
:
Note: * Only 0 can be written, to clear the flag.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR is initialized to H'84 by a reset, and in standby mode or module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE
Description
0
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DTC is activated by a TXI interrupt and writes data to TDR
1
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and data can be written to TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF
Description
0
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF = 1
•
When the DTC is activated by an RXI interrupt and reads data from RDR
1
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
6
5
RDRF
ORER
0
0
R/(W) *
R/(W) *
R/(W) *
4
3
FER
PER
TEND
0
0
R/(W) *
Rev. 5.00, 12/03, page 435 of 1088
2
1
0
MPB
MPBT
1
0
0
R
R
R/W
(Initial value)
(Initial value)
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