Phase Counting Mode - Renesas H8S/2319 series Hardware Manual

9.4.7

Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 9-8 shows the correspondence between external clock pins and channels.
Table 9-8 Phase Counting Mode Clock Input Pins
Channels
When channel 1 or 5 is set to phase counting mode
When channel 2 or 4 is set to phase counting mode
Example of Phase Counting Mode Setting Procedure: Figure 9-28 shows an example of the
phase counting mode setting procedure.
Phase counting mode
Select phase counting mode
Start count
<Phase counting mode>
Figure 9-28 Example of Phase Counting Mode Setting Procedure
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[2]
External Clock Pins
A-Phase B-Phase
TCLKA TCLKB
TCLKC TCLKD
Rev. 5.00, 12/03, page 355 of 1088