Full access
Burst access
T
T
T
T
T
T
T
1
2
3
1
2
1
2
φ
Only lower address changed
Address bus
CS0
AS
RD
Data bus
Read data
Read data
Read data
Figure 6-15 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
Rev. 5.00, 12/03, page 171 of 1088
