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6.1.3
Pin Configuration
Table 6-1 summarizes the pins of the bus controller.
Table 6-1
Bus Controller Pins
Name
Address strobe
Read
High write
Low write
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Chip select 5
Chip select 6
Chip select 7
Wait
Bus request
Bus request acknowledge
Bus request output
Symbol I/O
Function
AS
Output
Strobe signal indicating that address output
on address bus is enabled.
RD
Output
Strobe signal indicating that external space
is being read.
HWR
Output
Strobe signal indicating that external space
is to be written, and upper half (D
of data bus is enabled.
LWR
Output
Strobe signal indicating that external space
is to be written, and lower half (D
data bus is enabled.
CS0
Output
Strobe signal indicating that area 0 is
selected.
CS1
Output
Strobe signal indicating that area 1 is
selected.
CS2
Output
Strobe signal indicating that area 2 is
selected.
CS3
Output
Strobe signal indicating that area 3 is
selected.
CS4
Output
Strobe signal indicating that area 4 is
selected.
CS5
Output
Strobe signal indicating that area 5 is
selected.
CS6
Output
Strobe signal indicating that area 6 is
selected.
CS7
Output
Strobe signal indicating that area 7 is
selected.
WAIT
Input
Wait request signal when accessing
external 3-state access space.
BREQ
Input
Request signal that releases bus to
external device.
BACK
Output
Acknowledge signal indicating that bus has
been released.
BREQO Output
External bus request signal used when
internal bus master accesses external
space when external bus is released.
Rev. 5.00, 12/03, page 141 of 1088
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