Renesas H8S/2319 series Hardware Manual page 321

Bit 1—Address 21 Enable (A21E): Enables or disables address output 21 (A21). For details, see
section 8.2, Port 1.
Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A20). For details, see
section 8.2, Port 1.
Port Function Control Register 2 (PFCR2)
Bit : 7
—
Initial value : 0
R/W : R/W
PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to
H'30 by a reset, and in hardware standby mode. This bit is valid in modes 4 to 6.
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bit 5—CS167 Enable (CS167E): Enables or disables CS1, CS6, and CS7 output. Change the
CS167E setting only when the DDR bits are cleared to 0.
Bit 5
CS167E Description
CS1, CS6, and CS7 output disabled (can be used as I/O ports)
0
CS1, CS6, and CS7 output enabled
1
Bit 4—CS25 Enable (CS25E): Enables or disables CS2, CS3, CS4, and CS5 output. Change the
CS25E setting only when the DDR bits are cleared to 0. This bit is valid in modes 4 to 6.
Bit 4
CS25E Description
CS2, CS3, CS4, and CS5 output disabled (can be used as I/O ports)
0
CS2, CS3, CS4, and CS5 output enabled
1
Bit 3—AS Output Disable (ASOD): Enables or disables AS output. This bit is valid in modes 4
to 6. For details, see section 8.11, Port F.
Bits 2 to 0—Reserved: When read, these bits are always read as 0.
6 5
CS167E CS25E
—
0 1
R/W R/W R/W
4 3 2
ASOD —
1 0 0
R/W R
Rev. 5.00, 12/03, page 291 of 1088
1 0
— —
0 0
R R
(Initial value)
(Initial value)