Section 18 Clock Pulse Generator; Overview; Block Diagram - Renesas H8S/2319 series Hardware Manual

18.1

Overview

The chip has an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-
speed clock divider, and a bus master clock selection circuit.
In the chip, the CPG has a medium-speed mode in which the bus master runs on a medium-speed
clock and the other supporting modules run on the high-speed clock, and a function that allows the
medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip.
A clock from φ/2 to φ/32 can be selected.
18.1.1

Block Diagram

Figure 18-1 shows a block diagram of the clock pulse generator.
EXTAL
Oscillator
XTAL
Figure 18-1 Block Diagram of Clock Pulse Generator

Section 18 Clock Pulse Generator

Duty
adjustment
circuit
DIV
Medium-
speed clock
φ/2 to φ/32
divider
System clock Internal clock
to φ pin
to supporting
modules
Rev. 5.00, 12/03, page 769 of 1088
SCKCR
SCK2 to SCK0
Bus master
clock
selection
circuit
Bus master clock
to CPU and DTC