Renesas H8S/2319 series Hardware Manual page 801

• The division ratio set with bits SCK2 to SCK0 should be selected so as to fall within the
guaranteed operation range of clock cycle time tcyc given in the AC timing table in the
Electrical Characteristics section. Ensure that φ min = 2 MHz, and the condition φ < 2 MHz
does not arise.
• All internal modules basically operate on φ. Note, therefore, that time processing involving the
timers, the SCI, etc., will change when the division ratio changes. The wait time when software
standby is cleared will also change in line with a change in the division ratio.
• The division ratio can be changed while the chip is operating. The clock output from the φ pin
will also change when the division ratio is changed. The frequency of the clock output from
the φ pin in this case will be as follows:
φ = EXTAL × n
Where: EXTAL: Crystal resonator or external clock frequency
n:
• Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits
SCK2 to SCK0.
Bit 5
DIV Description
0 When bits SCK2 to SCK0 are set to other than high-speed mode, medium-speed
mode is set
1 When bits SCK2 to SCK0 are set to other than high-speed mode, a divided clock is
supplied to the entire chip
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): When the DIV bit is cleared to 0,
these bits select the medium-speed mode; when the DIV bit is set to 1, they select the division
ratio of the clock supplied to the entire chip.
Division ratio (n = φ/2, φ/4, or φ/8)
Rev. 5.00, 12/03, page 771 of 1088
(Initial value)