Timer Start Register (Tstr) - Renesas H8S/2319 series Hardware Manual

9.2.8

Timer Start Register (TSTR)

Bit : 7
—
Initial value : 0
R/W : —
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.
TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating
mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bits 7 and 6—Reserved: Must always be written with 0.
Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for
TCNT.
Bit n
CSTn Description
0 TCNTn count operation is stopped
1 TCNTn performs count operation
Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the
counter stops but the TIOC pin output compare output level is retained. If TIOR is written to
when the CST bit is cleared to 0, the pin output level will be changed to the set initial output
value.
9.2.9 Timer Synchro Register (TSYR)
Bit : 7
—
Initial value : 0
R/W : —
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: Must always be written with 0.
6 5
— CST5 CST4
0 0
— R/W R/W
6 5
— SYNC5 SYNC4
0 0
— R/W R/W
4 3 2
CST3 CST2
0 0 0
R/W R/W
4 3 2
SYNC3 SYNC2
0 0 0
R/W R/W
Rev. 5.00, 12/03, page 331 of 1088
1 0
CST1 CST0
0 0
R/W R/W
(Initial value)
n = 5 to 0
1 0
SYNC1 SYNC0
0 0
R/W R/W