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8.8.2
Register Configuration
Table 8-13 shows the port C register configuration.
Table 8-13 Port C Registers
Name
Port C data direction register
Port C data register
Port C register
Port C MOS pull-up control register
Note: * Lower 16 bits of the address.
Port C Data Direction Register (PCDDR)
Bit
:
7
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial value :
0
R/W
:
W
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
PCDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
• Modes 4 and 5
The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits.
• Mode 6 *
Setting PCDDR bits to 1 makes the corresponding port C pin address outputs, while clearing the
bits to 0 makes the pins input ports.
• Mode 7 *
Setting PCDDR bits to 1 makes the corresponding port C pins an output ports, while clearing the
bits to 0 makes the pins input ports.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Abbreviation
PCDDR
PCDR
PORTC
PCPCR
6
5
0
0
W
W
W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
R/W
H'00
4
3
2
0
0
0
W
W
Rev. 5.00, 12/03, page 261 of 1088
Address *
H'FEBB
H'FF6B
H'FF5B
H'FF72
1
0
0
0
W
W
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