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TCR3—Timer Control Register 3
Bit
:
7
CCLR2
Initial value
:
0
Read/Write
:
R/W
6
5
CCLR1
CCLR0
CKEG1
0
0
R/W
R/W
Note: The internal clock edge selection is valid when the input clock is
φ/4 or slower. This setting is ignored if φ/1 or overflow/underflow
on another channel is selected as the input clock.
Counter Clear
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input capture
1
0
TCNT cleared by TGRB compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
1
0
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input capture
1
0
TCNT cleared by TGRD compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
Notes: 1.
Synchronous operation setting is performed by setting the SYNC
bit in TSYR to 1.
2.
When TGRC or TGRD is used as a buffer register, TCNT is not
cleared because the buffer register setting has priority, and
compare match/input capture does not occur.
4
3
2
CKEG0
TPSC2
0
0
0
R/W
R/W
R/W
Timer Prescaler
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Clock Edge
0
0
Count at rising edge
1
Count at falling edge
1
Ñ
Count at both edges
Rev. 5.00, 12/03, page 945 of 1088
H'FE80
1
0
TPSC1
TPSC0
0
0
R/W
R/W
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
Internal clock: counts on φ/1024
Internal clock: counts on φ/256
Internal clock: counts on φ/4096
*1
*2
*2
*1
TPU3
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