Renesas H8S/2319 series Hardware Manual page 505

Renesas 16-bit single-chip microcomputer
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Serial clock
Serial data
TDRE
TEND
TXI interrupt
request generated
• Serial data reception (synchronous mode)
Figure 12-18 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to synchronous, be sure to check that
the ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor
receive operations will be possible.
Transfer direction
Bit 7
Bit 0
Data written to TDR
and TDRE flag
cleared to 0 in TXI
interrupt handling routine
1 frame
Figure 12-17 Example of SCI Transmit Operation
Bit 7
Bit 0
Bit 1
TXI interrupt
request generated
Rev. 5.00, 12/03, page 475 of 1088
Bit 6
Bit 7
TEI interrupt
request generated

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