Renesas H8S/2319 series Hardware Manual page 852

(4) Timing of On-Chip Supporting Modules
Table 20-16 Timing of On-Chip Supporting Modules
Condition C: V = 2.4 V to 3.6 V, AV
CC
0 V, φ = 2 MHz to 14 MHz, T
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
TPU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
8-bit timer Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
WDT Overflow output delay time
SCI Input clock
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
A/D Trigger input setup time
converter
Rev. 5.00, 12/03, page 822 of 1088
= 2.4 V to 3.6 V, V
CC
= –20°C to 75°C (regular specifications)
a
Symbol
t
PWD
t
PRS
t
PRH
t
TOCD
t
TICS
t
TCKS
Single-edge t
TCKWH
specification
Both-edge t
TCKWL
specification
t
TMOD
t
TMRS
t
TMCS
Single-edge t
TMCWH
specification
Both-edge t
TMCWL
specification
t
WOVD
Asynchronous t
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
= 2.4 V to AV
ref
Condition C
Min Max Unit
— 70 ns
40 — ns
40 — ns
— 70 ns
40 — ns
40 — ns
1.5 — t
cyc
2.5 — t
cyc
— 70 ns
40 — ns
40 — ns
1.5 — t
cyc
2.5 — t
cyc
— 70 ns
4 — t
cyc
6 — t
cyc
0.4 0.6 t
Scyc
— 1.5 t
cyc
— 1.5 t
cyc
— 70 ns
70 — ns
70 — ns
30 — ns
, V = AV =
CC SS SS
Test Conditions
Figure 20-13
Figure 20-14
Figure 20-15
Figure 20-16
Figure 20-18
Figure 20-17
Figure 20-19
Figure 20-20
Figure 20-21
Figure 20-22