Section 4 Exception Handling; Overview; Exception Handling Types And Priority; Exception Handling Operation - Renesas H8S/2319 series Hardware Manual

4.1

Overview

4.1.1

Exception Handling Types and Priority

As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4-1 Exception Types and Priority
Priority Exception Type
High Reset
1
Trace *
Interrupt
Trap instruction (TRAPA) *
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in the program
execution state.
4.1.2

Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as
follows:
1. The program counter (PC), condition code register (CCR), and extend register (EXR) are
pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.

Section 4 Exception Handling

Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued *
3
Started by execution of a trap instruction (TRAPA)
Rev. 5.00, 12/03, page 99 of 1088
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