Renesas H8S/2319 series Hardware Manual page 252

P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after
in software standby mode.
Port 1 Register (PORT1)
Bit : 7
P17
— *
Initial value :
R/W : R
Note: * Determined by state of pins P17 to P10.
PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 1 pins (P17 to P10) must always be performed on P1DR.
If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1
read is performed while P1DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT1 contents are determined by the pin states, as
P1DDR and P1DR are initialized. PORT1 retains its prior state after in software standby mode.
Port Function Control Register 1 (PFCR1)
Bit : 7
CSS17
Initial value : 0
R/W : R/W
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to
H'0F by a reset, and in hardware standby mode.
Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. For
details, see section 8.12, Port G.
Bit 6—CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. For
details, see section 8.12, Port G.
Bit 5—Port F1 Chip Select 5 Select (PF1CS5S): Selects enabling or disabling of CS5 output.
For details, see section 8.11, Port F.
Bit 4—Port F0 Chip Select 4 Select (PF0CS4S): Selects enabling or disabling of CS4 output.
For details, see section 8.11, Port F.
Rev. 5.00, 12/03, page 222 of 1088
6 5
P16 P15
— * — *
R R
6 5
CSS36 PF1CS5S PF0CS4S
0 0
R/W R/W
4 3
P14 P13
— * — *
R R
4 3
A23E
0 1
R/W R/W
2 1
P12 P11
— * — *
R R
2 1
A22E A21E
1 1
R/W R/W
0
P10
— *
R
0
A20E
1
R/W