Renesas H8S/2319 series Hardware Manual page 406

Contention between TGR Write and Compare Match: If a compare match occurs in the T
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 9-51 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
TCNT
TGR
Figure 9-51 Contention between TGR Write and Compare Match
Rev. 5.00, 12/03, page 376 of 1088
TGR write cycle
T T
1 2
TGR address
N N+1
N
TGR write data
Inhibited
M
2