Register Configuration - Renesas H8S/2319 series Hardware Manual

Table 17-48 (1) Register Configuration
Name
Flash code control status register
Flash program code select register
Flash erase code select register
Flash key code register
Flash MAT select register
Flash transfer destination address
register
System control register 2
RAM emulation register
Notes: 1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit.
(The value which can be read is always 0.)
2. The initial value at initiation in user mode or user program mode is H'00.
The initial value at initiation in user boot mode is H'AA.
3. SYSCR2 is dedicated to the F-ZTAT versions.
Table 17-48 (2) Parameter Configuration
Name
Download pass/fail result
Flash pass/fail result
Flash multipurpose address area
Flash multipurpose data destination
area
Flash erase block select
Flash program and erase frequency
control
Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid.
Rev. 5.00, 12/03, page 674 of 1088
Abbreviation R/W
R, W *
FCCS
FPCS R/W
FECS R/W
FKEY R/W
FMATS R/W
FTDAR R/W
3
SYSCR2 *
R/W
RAMER R/W
Abbreviation R/W
DPFR R/W
FPFR R/W
FMPAR R/W
FMPDR R/W
FEBS R/W
FPEFEQ R/W
Initial Value Address
1
H'00 H'FFC4
H'80
H'00 H'FFC5
H'00 H'FFC6
H'00 H'FFC8
2
H'00 *
H'FFC9
2
H'AA *
H'00 H'FFCA
H'00 H'FF42
H'00 H'FEDB
Initial Value Address
On-chip RAM *
Undefined
Undefined R0L of CPU
Undefined ER1 of CPU
Undefined ER0 of CPU
Undefined ER0 of CPU
Undefined ER0 of CPU