Renesas H8S/2319 series Hardware Manual page 193

Address bus
D
Read
D
Write
D
D
Note: n = 0 to 7
Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
φ
CSn
AS
RD
to D
15 8
to D
7 0
HWR
LWR
to D
15 8
to D
7 0
Bus cycle
T
1
High
High impedance
Valid
Rev. 5.00, 12/03, page 163 of 1088
T
2
Invalid
Valid