Renesas H8S/2319 series Hardware Manual page 706

Bits 6 and 5—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 4—Flash Memory Error (FLER): Indicates an error occurs during programming and erasing
flash memory.
When FLER is set to 1, flash memory enters the error protection state.
This bit is initialized at a power-on reset or in hardware standby mode.
When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the
damage to flash memory, the reset must be released after the reset period of 100 µs which is
longer than normal.
Bit 4
FLER Description
0 Flash memory operates normally
Programming/erasing protection for flash memory (error protection) is invalid.
[Clearing condition] At a power-on reset or in hardware standby mode
1 Indicates an error occurs during programming/erasing flash memory.
Programming/erasing protection for flash memory (error protection) is valid.
[Setting condition] See section 17.25.3, Error Protection.
Bits 3 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—Source Program Copy Operation (SCO): Requests the on-chip programming/erasing
program to be downloaded to the on-chip RAM.
When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically
downloaded in the on-chip RAM area specified by FTDAR.
In order to set this bit to 1, RAM emulation state must be canceled, H'A5 must be written to
FKEY, and this operation must be in the on-chip RAM.
Four NOP instructions must be executed immediately after setting this bit to 1.
Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1.
All interrupts are prohibited during programming and erasing. Interrupts must not occur in the user
system.
Rev. 5.00, 12/03, page 676 of 1088
(Initial value)