Renesas H8S/2319 series Hardware Manual page 393

Renesas 16-bit single-chip microcomputer
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Table 9-13 TPU Interrupts
Interrupt
Channel
Source
0
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
1
TGI1A
TGI1B
TCI1V
TCI1U
2
TGI2A
TGI2B
TCI2V
TCI2U
3
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
4
TGI4A
TGI4B
TCI4V
TCI4U
5
TGI5A
TGI5B
TCI5V
TCI5U
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
Description
TGR0A input capture/compare match
TGR0B input capture/compare match
TGR0C input capture/compare match
TGR0D input capture/compare match
TCNT0 overflow
TGR1A input capture/compare match
TGR1B input capture/compare match
TCNT1 overflow
TCNT1 underflow
TGR2A input capture/compare match
TGR2B input capture/compare match
TCNT2 overflow
TCNT2 underflow
TGR3A input capture/compare match
TGR3B input capture/compare match
TGR3C input capture/compare match
TGR3D input capture/compare match
TCNT3 overflow
TGR4A input capture/compare match
TGR4B input capture/compare match
TCNT4 overflow
TCNT4 underflow
TGR5A input capture/compare match
TGR5B input capture/compare match
TCNT5 overflow
TCNT5 underflow
DTC
Activation
Possible
Possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Rev. 5.00, 12/03, page 363 of 1088
Priority
High
Low

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