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8-Bit 3-State Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D
The LWR pin is fixed high. Wait states can be inserted.
φ
Address bus
CSn
D
to D
Read
15
D
to D
7
HWR
LWR
Write
D
to D
15
D
to D
7
Note: n = 0 to 7
Figure 6-7 Bus Timing for 8-Bit 3-State Access Space
T
1
AS
RD
8
0
8
0
to D
) of the data bus is used.
15
8
Bus cycle
T
2
High
Valid
High impedance
Rev. 5.00, 12/03, page 161 of 1088
T
3
Valid
Invalid
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