Renesas H8S/2319 series Hardware Manual page 710

(6) Flash Transfer Destination Address Register (FTDAR)
FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make
settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which
points to the start address (H'FFBC00) in on-chip RAM.
Bit : 7
TDER
Initial value : 0
R/W : R/W
Bit 7—Transfer Destination Address Setting Error: This bit is set to 1 when there is an error in
the download start address set by bits 6 to 0 (TDA6 to TDA0). Whether the address setting is
erroneous or not is judged by checking whether the setting of TDA6 to TDA0 is between the range
of H'00 and H'03 after setting the SCO bit in FCCS to 1 and performing download. Before setting
the SCO bit to 1 be sure to set the FTDAR value between H'00 to H'03 as well as clearing this bit
to 0.
Bit 7
TDER Description (Return Value after Download)
0 Setting of TDA6 to TDA0 is normal
1 Setting of TDER and TDA4 to TDA0 is H'04 to H'FF and download has been
aborted
Bits 6 to 0—Transfer Destination Address (TDA6 to TDA0): These bits specify the download
start address. A value from H'00 to H'03 can be set to specify the download start address in on-
chip RAM in 4-kbyte units.
A value from H'04 to H'7F cannot be set. If such a value is set, the TDER bit (bit 7) in this register
is set to 1 to prevent download from being executed.
Bits 6 to 0
TDA6 to
TDA0 Description
H'00 Download start address is set to H'FFBC00
H'01 Download start address is set to H'FFCC00
H'02 Download start address is set to H'FFDC00
H'03 Download start address is set to H'FFEC00
H'04 to H'7F Setting prohibited. If this value is set, the TDER bit (bit 7) is set to 1 to abort the
download processing.
Rev. 5.00, 12/03, page 680 of 1088
6 5
TDA6 TDA5 TDA4
0 0
R/W R/W
4 3
TDA3 TDA2
0 0
R/W R/W
2 1
TDA1 TDA0
0 0
R/W R/W R/W
(Initial value)
0
0