Renesas H8S/2319 series Hardware Manual page 840

Item
SCI Input clock
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
A/D Trigger input setup time
converter
φ
Ports 1 to 4,
A to G
(read)
Ports 1 to 3,
A to G
(write)
Rev. 5.00, 12/03, page 810 of 1088
Symbol
Asynchronous t
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
T
1
Figure 20-13 I/O Port Input/Output Timing
Condition A Condition B
Min Max Min
4 — 4
6 — 6
0.4 0.6 0.4
— 1.5 —
— 1.5 —
— 50 —
50 — 40
50 — 40
30 — 30
T
2
t t
PRS PRH
Test
Max Unit Conditions
— t Figure 20-20
cyc
—
0.6 t
Scyc
1.5 t
cyc
1.5 t
cyc
40 ns Figure 20-21
— ns
— ns
— ns Figure 20-22
t
PWD