Renesas H8S/2319 series Hardware Manual page 419

When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channel 0 and channel 1.
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the
TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting.
10.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)
TCSR0
Bit : 7
CMFB
Initial value : 0
R/(W) *
R/W :
TCSR1
Bit : 7
CMFB
Initial value : 0
R/(W) *
R/W :
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and
control compare match output.
TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode.
Description
Clock input disabled
Internal clock, counted at falling edge of φ/8
Internal clock, counted at falling edge of φ/64
Internal clock, counted at falling edge of φ/8192
For channel 0: count at TCNT1 overflow signal *
For channel 1: count at TCNT0 compare match A *
External clock, counted at rising edge
External clock, counted at falling edge
External clock, counted at both rising and falling edges
6 5
CMFA OVF
0 0
R/(W) * R/(W) *
6 5
CMFA OVF
0 0
R/(W) * R/(W) *
4 3
ADTE OS3
0 0
R/W R/W
4 3
— OS3
1 0
— R/W
Rev. 5.00, 12/03, page 389 of 1088
(Initial value)
2 1
OS2 OS1 OS0
0 0
R/W R/W R/W
2 1
OS2 OS1 OS0
0 0
R/W R/W R/W
0
0
0
0