Table of Contents
Advertisement
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9-46 shows the timing
for status flag clearing by the CPU, and figure 9-47 shows the timing for status flag clearing by the
DTC.
φ
Address
Write signal
Status flag
Interrupt
request
signal
Figure 9-46 Timing for Status Flag Clearing by CPU
φ
Address
Status flag
Interrupt
request
signal
Figure 9-47 Timing for Status Flag Clearing by DTC Activation
Rev. 5.00, 12/03, page 372 of 1088
TSR write cycle
T
T
1
2
TSR address
DTC
read cycle
write cycle
T
T
T
1
2
1
Destination
Source address
address
DTC
T
2
Advertisement
Table of Contents
