Pin Functions - Renesas H8S/2319 series Hardware Manual

Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A23). This bit is valid
in modes 4 to 6.
Bit 3
A23E Description
0 P13DR is output when P13DDR = 1
1 A23 is output when P13DDR = 1
Bit 2—Address 22 Enable (A22E): Enables or disables address output 22 (A22). This bit is valid
in modes 4 to 6.
Bit 2
A22E Description
0 P12DR is output when P12DDR = 1
1 A22 is output when P12DDR = 1
Bit 1—Address 21 Enable (A21E): Enables or disables address output 21 (A21). This bit is valid
in modes 4 to 6.
Bit 1
A21E Description
0 P11DR is output when P11DDR = 1
1 A21 is output when P11DDR = 1
Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A20). This bit is valid
in modes 4 to 6.
Bit 0
A20E Description
0 P10DR is output when P10DDR = 1
1 A20 is output when P10DDR = 1
8.2.3

Pin Functions

Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0,
TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and address output pins
(A23 to A20). Port 1 pin functions are shown in table 8-3.
Rev. 5.00, 12/03, page 223 of 1088
(Initial value)
(Initial value)
(Initial value)
(Initial value)