Block Diagram - Renesas H8S/2319 series Hardware Manual

6.1.2

Block Diagram

Figure 6-1 shows a block diagram of the bus controller.
CS0 to CS7
External bus control signals
BREQ
BACK
BREQO
WAIT
Rev. 5.00, 12/03, page 140 of 1088
Area decoder
controller
Wait
controller
Bus arbiter
Figure 6-1 Block Diagram of Bus Controller
ABWCR
ASTCR
BCRH
BCRL
Bus
WCRH
WCRL
CPU bus request signal
DTC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
Internal
address bus
Internal control
signals
Bus mode signal