Renesas H8S/2319 series Hardware Manual page 336

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both
edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Bit 4 Bit 3
CKEG1 CKEG0
0 0
1
1 —
Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected.
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter
clock. The clock source can be selected independently for each channel. Table 9-4 shows the clock
sources that can be set for each channel.
Table 9-4 TPU Clock Sources
φ φ φ φ /1 φ φ φ φ /4 φ φ φ φ /16 φ φ φ φ /64 φ φ φ φ /256 φ φ φ φ /1024 φ φ φ φ /4096
Channel
0
1
2
3
4
5
Legend:
: Setting
Blank : No setting
Rev. 5.00, 12/03, page 306 of 1088
Description
Count at rising edge
Count at falling edge
Count at both edges
Internal Clock External Clock
TCLKA TCLKB TCLKC TCLKD Channel
(Initial value)
Overflow/
Underflow
on Another