Operation - Renesas H8S/2319 series Hardware Manual

5.6.3

Operation

The interrupt controller has three main functions in DTC control.
Selection of Interrupt Source: For interrupt sources, it is possible to select DTC activation
request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC has performed the specified number of data transfers and the transfer counter value
is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data
transfer.
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table,
for the respective priorities.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5-11 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCERA to DTCERE, and the DISEL bit of MRB in the DTC.
Table 5-11 Interrupt Source Selection and Clearing Control
Settings
DTC
DTCE
0
1
Legend:
: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
: The relevant interrupt is used. The interrupt source is not cleared.
X : The relevant interrupt cannot be used.
× :
Don't care
Usage Note: SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to
the prescribed register, and are not dependent upon the DTA bit or DISEL bit.
DISEL
×
0
1
Interrupt Source Selection/Clearing Control
DTC
X
Rev. 5.00, 12/03, page 137 of 1088
CPU
X