Block Diagram - Renesas H8S/2319 series Hardware Manual

7.1.2

Block Diagram

Figure 7-1 shows a block diagram of the DTC.
The DTC's register information is stored in the on-chip RAM * . A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt controller
Interrupt
request
CPU interrupt
request
Legend:
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERE
DTVECR
Rev. 5.00, 12/03, page 184 of 1088
DTC
: DTC mode registers A and B
: DTC transfer count registers A and B
: DTC source address register
: DTC destination address register
: DTC enable registers A to E
: DTC vector register
Figure 7-1 Block Diagram of DTC
Internal address bus
Internal data bus
On-chip
RAM