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Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T
state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
2
data prior to the write.
Figure 9-52 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR
Figure 9-52 Contention between Buffer Register Write and Compare Match
TGR write cycle
T
T
1
2
Buffer register
address
N
M
N
Rev. 5.00, 12/03, page 377 of 1088
Buffer register write data
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