Table of Contents
Advertisement
2.6
Instruction Set
2.6.1
Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in
table 2-1.
Table 2-1
Instruction Classification
Function
Data transfer
Arithmetic
operations
Logic operations
Shift
Bit manipulation
Branch
System control
Block data transfer
Legend: B: byte size; W: word size; L: longword size.
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in the H8S/2319 and H8S/2318 Groups.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Instructions
MOV
1
1
POP *
, PUSH *
LDM, STM
MOVFPE, MOVTPE *
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
4
TAS *
AND, OR, XOR, NOT
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
2
Bcc *
, JMP, BSR, JSR, RTS
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
EEPMOV
3
Size
BWL
WL
L
B
BWL
B
BWL
L
BW
WL
B
BWL
B
—
—
Total
Rev. 5.00, 12/03, page 39 of 1088
Types
5
19
4
8
14
5
9
1
65
Advertisement
Table of Contents
