Register Configuration - Renesas H8S/2319 series Hardware Manual

8.9.2

Register Configuration

Table 8-15 shows the port D register configuration.
Table 8-15 Port D Registers
Name
Port D data direction register
Port D data register
Port D register
Port D MOS pull-up control register
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
Bit : 7
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value : 0
R/W : W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 4 to 6 *
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
• Mode 7 *
Setting PDDDR bits to 1 makes the corresponding port D pins output ports, while clearing the
bits to 0 makes the pins input ports.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Abbreviation
PDDDR
PDDR
PORTD
PDPCR
6 5
0 0
W W W
R/W Initial Value
W H'00
R/W H'00
R Undefined
R/W H'00
4 3 2
0 0 0
W W
Rev. 5.00, 12/03, page 267 of 1088
Address *
H'FEBC
H'FF6C
H'FF5C
H'FF73
1 0
0 0
W W