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8.10.2
Register Configuration
Table 8-17 shows the port E register configuration.
Table 8-17 Port E Registers
Name
Port E data direction register
Port E data register
Port E register
Port E MOS pull-up control register
Note: * Lower 16 bits of the address.
Port E Data Direction Register (PEDDR)
Bit
:
7
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
Initial value :
0
R/W
:
W
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 4 to 6 *
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit
to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the
pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is
ignored, and port E is designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller.
• Mode 7 *
Setting PEDDR bits to 1 makes the corresponding port E pins output ports, while clearing the
bits to 0 makes the pins input ports.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Abbreviation
PEDDR
PEDR
PORTE
PEPCR
6
5
0
0
W
W
W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
R/W
H'00
4
3
2
0
0
0
W
W
Rev. 5.00, 12/03, page 273 of 1088
Address *
H'FEBD
H'FF6D
H'FF5D
H'FF74
1
0
0
0
W
W
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