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17.23.2 Programming/Erasing Interface Parameter
The programming/erasing interface parameter specifies the operating frequency, storage place for
program data, programming destination address, and erase block and exchanges the processing
result for the downloaded on-chip program. This parameter uses the general registers of the CPU
(ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a power-on reset or in
hardware standby mode.
When download, initialization, or on-chip program is executed, registers of the CPU except for
R0L are stored. The return value of the processing result is written in R0L. Since the stack area is
used for storing the registers except for R0L, the stack area must be saved at the processing start.
(A maximum size of a stack area to be used is 128 bytes.)
The programming/erasing interface parameter is used in the following four items.
(1) Download control
(2) Initialization before programming or erasing
(3) Programming
(4) Erasing
These items use different parameters. The correspondence table is shown in table 17-50.
Here the FPFR parameter returns the results of initialization processing, programming processing,
or erasing processing, but the meaning of the bits differs depending on the type of processing. For
details, refer to the FPFR descriptions for the individual processes.
Rev. 5.00, 12/03, page 681 of 1088
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