Register Descriptions; Dtc Mode Register A (Mra) - Renesas H8S/2319 series Hardware Manual

7.2

Register Descriptions

7.2.1

DTC Mode Register A (MRA)

Bit : 7
SM1
Initial value : Unde-
fined
R/W : —
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7 Bit 6
SM1 SM0
0 —
1 0
1
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5 Bit 4
DM1 DM0
0 —
1 0
1
Rev. 5.00, 12/03, page 186 of 1088
6 5
SM0 DM1
Unde- Unde-
fined fined
— —
Description
SAR is fixed
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Description
DAR is fixed
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
4 3
DM0 MD1
Unde- Unde- Unde-
fined fined
— —
2 1
MD0 DTS
Unde- Unde-
fined fined fined
— —
0
Sz
—