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17.4.9
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 17-6.
In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set
to 1 in SYSCR2 (except RAMER).
Table 17-6 Flash Memory Registers
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
System control register 2
RAM emulation register
Notes: 1. Lower 16 bits of the address.
2. Flash memory. Registers selection is performed by the FLSHE bit in system control
register 2 (SYSCR2).
3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid. Writes are also disabled when the FWE bit is cleared to 0 in
FLMCR1.
4. When a high level is input to the FWE pin, the initial value is H'80.
5. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, these registers are initialized to H'00.
6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
for these registers, the access requiring 2 states.
7. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM
versions this register will return an undefined value if read, and cannot be modified.
Rev. 5.00, 12/03, page 566 of 1088
Abbreviation R/W
6
FLMCR1 *
R/W *
6
FLMCR2 *
R/W *
6
EBR1 *
R/W *
6
EBR2 *
R/W *
7
SYSCR2 *
R/W
RAMER
R/W
Initial Value
3
4
H'00 *
3
H'00
3
5
H'00 *
3
5
H'00 *
H'00
H'00
1
Address *
2
H'FFC8 *
2
H'FFC9 *
2
H'FFCA *
2
H'FFCB *
H'FF42
H'FEDB
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