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SP
(c) Interrupt control mode 0
Note: * Ignored when returning.
Figure 2-13 Stack Structure after Exception Handling (Examples)
2.8.4
Program Execution State
In this state the CPU executes program instructions in sequence.
2.8.5
Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts.
There is one other bus master in addition to the CPU: the data transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
2.8.6
Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode,
software standby mode, and hardware standby mode. There are also two other power-down
modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other
bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation
of individual modules, other than the CPU. For details, refer to section 19, Power-Down Modes.
CCR
PC
(24 bits)
SP
EXR
Reserved*
CCR
PC
(24 bits)
(d) Interrupt control mode 2
Rev. 5.00, 12/03, page 63 of 1088
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